1. Field of the Invention
The present invention relates to a method for fabricating an interconnect structure and an interconnect opening. More particularly, the present invention relates to a method for fabricating a single-damascene structure, a dual-damascene structure, and an opening thereof.
2. Description of Related Art
With the advancement of semiconductor technologies, the dimensions of semiconductor devices continuously reduce to the deep sub-micron territory. As the level of integration of integrated circuits increases, the surface of a chip is inadequate to accommodate all the required interconnects. In order to accommodate the increase of interconnects after the miniaturization of semiconductor devices, the design of a multilevel interconnect is used in ultra large scale integration circuits (ULSI).
In general, the multilevel interconnection is formed using a damascene process, which includes the single-damascene process or the dual-damascene process. Currently, the damascene process that involves the defining of a trench (or opening) in a dielectric layer requires forming a titanium nitride layer on the dielectric layer first. Thereafter, a photoresist layer with a trench (or opening) pattern is formed over the titanium nitride layer. The trench (or opening) pattern of the photoresist layer is then transferred to the titanium nitride layer. Further using the titanium nitride layer with the trench (or opening) pattern as a hark mask, a trench (or opening) is then defined in the dielectric layer. Limited by the yellow light process, a plasma-enhanced oxide (PE-oxide) layer is typically formed on the titanium nitride layer to increase the process window, wherein both the titanium nitride layer and the PE-oxide layer serve as the hard mask layer in the damascene process.
However, there are problems still needed to be resolved in a damascene process. For example, before defining the trench (or opening) in the dielectric layer, two etching steps are performed in order to define the trench (or opening) pattern in the hard mask layer. The two etching steps include a first etching step and a second etching step. The first etching step includes removing a portion of the PE-oxide layer until the surface of the titanium nitride layer is exposed using the photoresist layer as a mask. The second etching step includes etching a portion of the titanium nitride layer until the surface of the dielectric layer is exposed. Accordingly, the conventional damascene process requires performing multiple steps, and thus a longer cycle time is resulted.